This invention relates to semiconductor device fabrication and more particularly to a method for forming a relatively shallow and highly concentrated impurity layer adjacent to the surface of a semiconductive region.
In the fabrication of semiconductor devices, such as integrated circuits, it is generally required that significant dopant impurities be introduced into a surface of a semiconductive region in order to form a surface impurity layer having electrical characteristics which are different from those of the rest of the region. By using appropriate impurities in appropriate amounts there may be formed a surface layer of the opposite conductivity type to that of the rest of the region, a surface layer of the same conductivity type as the rest of the region but having a lower resistivity or a surface layer of the same conductivity type as the rest of the region but having a higher resistivity. This invention provides a novel and advantageous method for forming such a surface impurity layer.
For example, in the fabrication of integrated circuits, it is generally desirable to reduce the lateral dimensions of circuit features to achieve a higher packing density, improved performance and a lower power dissipation. Recently, the development of improved lithographic and etching techniques have made it possible to form circuit features having lateral dimensions of less than 1 .mu.m. However, in order to fabricate integrated circuits having such submicron features, it is necessary and/or desirable to provide relatively shallow surface impurity layers having relatively low sheet resistances.
In the case of metal-oxide-semiconductor (MOS) circuits, a reduction in the channel length of a MOS transistor necessitates a corresponding reduction in the depths of the source/drain regions of the transistor in order to avoid unwanted short channel effects and excessive parasitic capacitances. For example, in an N-channel MOS transistor having an effective channel length of 0.5 .mu.m, a gate oxide thickness of 250 Angstroms and a channel doping concentration of 4.times.10.sup.16 cm.sup.-3, short channel effects are substantially avoided if the depths of the source/drain regions are less than 1000 Angstroms below the surface of the channel. In addition, it is also desirable for the source/drain regions to have a relatively low sheet resistance (e.g., less than 70 ohms per square) to permit rapid operation of the transistor.
In the case of bipolar circuits, a reduction in the lateral spacings between the various regions of a bipolar transistor necessitates a corresponding reduction in the respective depths of those regions. For example, in a vertical bipolar transistor structure having a minimum feature size of 1 .mu.m, it is desirable that the emitter region be less than 2000 Angstroms in order to insure control over the base width and the total base charge. Moreover, it is also desirable for the emitter region to have a relatively low sheet resistance in order to provide a high minority carrier injection efficiency and to minimize the emitter crowding effect.
In the prior art surface impurity layers are most frequently formed by either conventional diffusion or ion implantation. In a conventional diffusion process impurities are first introduced into a semiconductor surface by diffusion from an appropriate predeposition source, such as a heavily doped semiconductor oxide layer or polycrystalline semiconductor layer in contact with the surface. The impurities are then thermally driven to a desired depth in a separate drive-in step. Although surface impurity layers as shallow as 500 Angstroms may be formed by conventional diffusion by using relatively low temperatures and short diffusion times, such layers tend to have relatively low impurity concentrations and therefore relatively high sheet resistances. Since the rate of transport of impurities into a semiconductor by conventional diffusion is generally limited by the solid solubility of the impurities in the semiconductor at the diffusion temperature, conventional diffusion has the disadvantage of ordinarily not being able to provide a shallow layer with a sufficiently high impurity concentration to result in a relatively low sheet resistance.
In the case of ion implantation impurities are introduced into a semiconductor surface by bombarding the surface with a beam of ionized impurities whose kinetic energy is in the range of one to several hundred kilovolts. Since the rate of implantation is largely independent of solid solubility of the impurities in the semiconductor and the depth of implantation can be precisely controlled, ion implantation can provide relatively shallow impurity layers having much higher impurity concentrations than those obtainable by conventional diffusion. However, ion implantation generally causes lattice damage which significantly lowers the carrier mobility in an implanted region. Consequently, ion implantation has a disadvantage in that even a highly concentrated impurity layer formed thereby generally has a relatively high sheet resistance unless the lattice damage caused by ion implantation is substantially repaired by an appropriate post-implantation annealing treatment. Since such an annealing treatment normally requires heating of the implanted layer for a relatively long time or at a relatively high temperature, the implanted layer will diffuse to a relatively large depth during the annealing treatment. For that reason it is difficult to form by ion implantation a surface impurity layer which is relatively shallow (e.g., less than 2000 Angstroms) and which has a relatively low sheet resistance (e.g., less than 70 ohms per square).
Therefore, a need clearly exists for a method for forming a surface impurity layer which has a lower sheet resistance than a layer of comparable depth formed by conventional diffusion and which has a shallower depth than a layer of comparable sheet resistance formed by ion implantation.